The present invention relates to logic circuit analyzers and, more particularly, to a test unit of an overall analyzer for testing or identifying the output signals at various points in a logic circuit.
A large number of logic components such as gates are implemented on integrated circuits and a large number of integrated circuits constituting a logic circuit or system commonly are produced on a printed circuit (PC) board. As is known, this logic circuit can fail as a result of, for example, manufacturing defects or improper operation of the circuit. As a result of these failures, improper logic states can be produced at various output points of the failed circuit.
A large variety of logic circuit analyzers have been developed to test the logic components of the logic circuit. Typically, the analyzers have a combined test unit and display. A single probe of the test unit is placed on a test point of the logic circuit at the output of the logic component being tested. The test probe senses the output signal at the test point, which is then fed by the test unit to the display where it is displayed on the screen. These analyzers may have multiple test probes which can be applied to multiple test points for displaying simultaneously corresponding output signals on respective traces of the display. Should one or more of the logic components have failed, this will be indicated by the improper output signal or signals being displayed on the oscilloscope.
A logic circuit state indicator is disclosed in U.S. Pat. No. 3,602,810, in which a plurality of output signals from different test points of a logic circuit are displayed simultaneously on a single trace of an oscilloscope. This is accomplished by using a plurality of probes and a plurality of weighted resistors connected, respectively, to the probes. The resistors are also connected in common to a summing junction which is coupled to the oscilloscope. The test probes are placed on individual test points, with the output signals being fed through the weighted resistors to the summing junction for display on the oscilloscope. By means of the weighted resistors, the output signals from each test point appearing on the single trace can be distinguished from one another, whereby a corresponding failed component can be determined.
A disadvantage with the logic circuit state indicator of the above-mentioned patent is that it is designed only for use in testing a predetermined logic circuit. That is, the logic circuit state indicator is built into a logic circuit whose output signals or pulses at various test points are known at any instant of time. If the pulse waveform on the oscilloscope is not the expected waveform, then component failure can be determined. This logic circuit state indicator is not a general logic circuit analyzer which can be employed to determine component failures in any logic circuit.